1. Field of the Invention
This invention relates generally to phase locked loop (PLL) based microprocessors, and more specifically, to a microprocessor clock control circuit that adjusts the frequency of the PLL based microprocessor and method therefor.
2. Description of the Prior Art
Microprocessors with internal PLL loops present unique problems for power management. In order to change the frequency of these types of processors, the following needs to be done: assert a stop clock and wait for a stop grant cycle, change the frequency of the microprocessor, and wait for the microprocessor's internal PLL to lock onto a new frequency which generally takes one millisecond.
The above procedure for changing the frequency of the microprocessor is not optimal for several reasons. First, during the one millisecond it takes for the microprocessor's internal PLL to lock on to a new frequency, power is consumed and no work is done. Second, interrupt and direct memory access (DMA) latency issues exist such as loss of data, data corruption, or even system failure. Third, the PLL lock time has the effect of causing the power management to be overly cautious in controlling the clock. For example, assume the system is running the microprocessor at a maximum frequency. When it becomes desirable to enter a lower power state, the system must be able to tolerate the 1 millisecond latency. In a worst case situation, the latency is greater than 2 milliseconds assuming there is a 1 millisecond PLL relock time. Assume that the processor is running at a maximum frequency and a decision is made, either by hardware or software, to slow the clock. At the same instance that the slow down process is started, a system condition changes which requires the system to return to the maximum frequency. In this case, the microprocessor would begin the process of changing the speed of the clock. After the clock rate is changed, a 1 millisecond delay is required for the PLL relock time. When the microprocessor resumes operation after the PLL relock time, it would discover that a new demand has been made to alter the frequency. This discovery, from an interrupt, a system management interrupt (SMI), or software poll, would occur at the new slower microprocessor rate. It is also possible that additional data and/or work has accumulated during the 1 millisecond delay which was required for the clock to change. Returning the system to the maximum frequency will take an additional 1 millisecond. The performance impact is therefor 2 milliseconds of dead time and some execution of commands at a slower microprocessor rate.
Therefore a need exist to provide an improved microprocessor or a circuit external to the existing microprocessor that can overcome this requirement. The improved microprocessor or microprocessor clock control circuit must be capable of continually adjusting its frequency based on the current system operating conditions.